lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <98014597-29BA-4D02-8137-4E399955F4FD@aosc.io>
Date:   Mon, 22 May 2017 17:41:52 +0800
From:   Icenowy Zheng <icenowy@...c.io>
To:     Marc Zyngier <marc.zyngier@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Rob Herring <robh+dt@...nel.org>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Chen-Yu Tsai <wens@...e.org>, Lee Jones <lee.jones@...aro.org>,
        Liam Girdwood <lgirdwood@...il.com>,
        Mark Brown <broonie@...nel.org>
CC:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-sunxi@...glegroups.com
Subject: Re: [PATCH v6 2/9] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC



于 2017年5月22日 GMT+08:00 下午5:39:22, Marc Zyngier <marc.zyngier@....com> 写到:
>On 18/05/17 08:16, Icenowy Zheng wrote:
>> Add support for the newly imported compatible for the A64 R_INTC in
>> irq-sunxi-nmi driver.
>> 
>> Signed-off-by: Icenowy Zheng <icenowy@...c.io>
>> ---
>> Changes in v5:
>> - Fix A64 R_INTC compatible.
>> 
>>  drivers/irqchip/irq-sunxi-nmi.c | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>> 
>> diff --git a/drivers/irqchip/irq-sunxi-nmi.c
>b/drivers/irqchip/irq-sunxi-nmi.c
>> index 668730c5cb66..5559c1d593bf 100644
>> --- a/drivers/irqchip/irq-sunxi-nmi.c
>> +++ b/drivers/irqchip/irq-sunxi-nmi.c
>> @@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs
>= {
>>  	.enable	= 0x04,
>>  };
>>  
>> +static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
>> +	.ctrl	= 0x0c,
>> +	.pend	= 0x10,
>> +	.enable	= 0x40,
>> +};
>> +
>
>Magic values? Even if no #define is provided, a pointer to the
>corresponding documentation would be appreciated (assuming
>documentation
>exists).

No documents is available for A64 R_INTC.

>
>>  static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc,
>u32 off,
>>  				      u32 val)
>>  {
>> @@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct
>device_node *node,
>>  	return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
>>  }
>>  IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi",
>sun9i_nmi_irq_init);
>> +
>> +static int __init sun50i_nmi_irq_init(struct device_node *node,
>> +				     struct device_node *parent)
>> +{
>> +	return sunxi_sc_nmi_irq_init(node, &sun50i_reg_offs);
>> +}
>> +IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc",
>sun50i_nmi_irq_init);
>> 
>
>Apart from the above:
>
>Acked-by: Marc Zyngier <marc.zyngier@....com>
>
>Let me know how you want this to be merged.

I think it can just go via IRQ subsystem.

>
>Thanks,
>
>	M.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ