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Message-ID: <CALCETrUCsWxLNGTN=CUZWWagghEwVdPYr6UFzwTENFTr6JTfRA@mail.gmail.com>
Date: Fri, 26 May 2017 00:21:41 -0700
From: Andy Lutomirski <luto@...nel.org>
To: Kevin Easton <kevin@...rana.org>
Cc: Andy Lutomirski <luto@...nel.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Andrew Morton <akpm@...ux-foundation.org>,
"the arch/x86 maintainers" <x86@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, Andi Kleen <ak@...ux.intel.com>,
Dave Hansen <dave.hansen@...el.com>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
linux-mm <linux-mm@...ck.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging
On Thu, May 25, 2017 at 9:18 PM, Kevin Easton <kevin@...rana.org> wrote:
> (If it weren't for that, maybe you could point the last entry in the PML4
> at the PML4 itself, so it also works as a PML5 for accessing kernel
> addresses? And of course make sure nothing gets loaded above
> 0xffffff8000000000).
This was an old trick done for a very different reason: it lets you
find your page tables at virtual addresses that depend only on the VA
whose page table you're looking for and the top-level slot that points
back to itself. IIRC Windows used to do this for its own memory
management purposes. A major downside is that an arbitrary write
vulnerability lets you write your own PTEs without any guesswork.
--Andy
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