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Message-ID: <20170608141023.37759527@free-electrons.com>
Date: Thu, 8 Jun 2017 14:10:23 +0200
From: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To: Rob Herring <robh@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Kumar Gala <galak@...eaurora.org>,
Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Gregory Clement <gregory.clement@...e-electrons.com>,
Nadav Haklai <nadavh@...vell.com>,
Hanna Hawa <hannah@...vell.com>,
Yehuda Yitschak <yehuday@...vell.com>,
Antoine Tenart <antoine.tenart@...e-electrons.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT
binding for the Marvell GICP
Hello,
On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote:
> On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> > This commit adds the Device Tree binding documentation for the Marvell
> > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> > using memory transactions. It is used by the ICU unit in the Marvell
> > CP110 block to turn wired interrupts inside the CP into SPI interrupts
> > at the GIC level in the AP.
>
> Sounds like an MSI block?
Marc Zyngier answered on this (much better than I could have done).
> > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> > + for this GICP
>
> These are base+size?
Correct. Does your question suggest that I should update the binding
document to make this explicit?
Thanks,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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