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Message-ID: <20170608163213.GA2216@red-moon>
Date: Thu, 8 Jun 2017 17:32:13 +0100
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To: Geetha sowjanya <gakula@...iumnetworks.com>, lv.zheng@...el.com,
robin.murphy@....com, rjw@...ysocki.net
Cc: will.deacon@....com, hanjun.guo@...aro.org, sudeep.holla@....com,
iommu@...ts.linux-foundation.org, robert.moore@...el.com,
jcm@...hat.com, linux-kernel@...r.kernel.org,
robert.richter@...ium.com, catalin.marinas@....com,
sgoutham@...ium.com, linux-arm-kernel@...ts.infradead.org,
linux-acpi@...r.kernel.org, geethasowjanya.akula@...il.com,
devel@...ica.org, linu.cherian@...ium.com,
Charles.Garcia-Tobin@....com, robh@...nel.org
Subject: Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote:
> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
> SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
> SMMU doesnt support unique IRQ lines and also MSI for gerror,
> eventq and cmdq-sync
>
> The following patchset does software workaround for these two erratas.
>
> This series is based on patchset.
> https://www.spinics.net/lists/arm-kernel/msg578443.html
Yes so it is not standalone. How are we going to merge these
ACPI IORT/ACPICA/SMMU patches - inclusive of:
[1] https://www.spinics.net/lists/arm-kernel/msg586458.html
Rafael, do ACPICA patches go upstream via the ACPI tree pull request ?
To remove dependency on ACPICA changes this series needs updating
anyway and for [1] above I think the only solution is for all the
patches to go via the ACPI tree (if ACPICA updates go upstream with it).
Thanks,
Lorenzo
> Changes since v6:
> - Changed device tree compatible string to vendor specific.
> - Rebased on Robin's latest "Update SMMU models for IORT rev. C" v2 patch.
> https://www.spinics.net/lists/arm-kernel/msg582809.html
>
> Changes since v5:
> - Rebased on Robin's "Update SMMU models for IORT rev. C" patch.
> https://www.spinics.net/lists/arm-kernel/msg580728.html
> - Replaced ACPI_IORT_SMMU_V3_CAVIUM_CN99XX macro with ACPI_IORT_SMMU_CAVIUM_CN99XX
>
> Changes since v4:
> - Replaced all page1 offset macros ARM_SMMU_EVTQ/PRIQ_PROD/CONS with
> arm_smmu_page1_fixup(ARM_SMMU_EVTQ/PRIQ_PROD/CONS, smmu)
>
> Changes since v3:
> - Merged patches 1, 2 and 4 of Version 3.
> - Modified the page1_offset_adjust() and get_irq_flags() implementation as
> suggested by Robin.
>
> Changes since v2:
> - Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with
> new SMMU option used to enable errata workaround.
>
> Changes since v1:
> - Since the use of MIDR register is rejected and SMMU_IIDR is broken on this
> silicon, as suggested by Will Deacon modified the patches to use ThunderX2
> SMMUv3 IORT model number to enable errata workaround.
>
> Geetha Sowjanya (1):
> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
>
> Linu Cherian (2):
> ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3
> model
> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum
> #74
>
> Documentation/arm64/silicon-errata.txt | 2 +
> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++
> drivers/acpi/arm64/iort.c | 10 ++-
> drivers/iommu/arm-smmu-v3.c | 93 ++++++++++++++++----
> 4 files changed, 91 insertions(+), 20 deletions(-)
>
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