linux-kernel - Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CANHdaib+mNgVS7g=vft-5ZtabSKkeyXO7Jp1EQhL3jduhu5F7g@mail.gmail.com>
Date:   Fri, 9 Jun 2017 11:30:53 +0530
From:   Geetha Akula <geethasowjanya.akula@...il.com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Cc:     Geetha sowjanya <gakula@...iumnetworks.com>,
        Will Deacon <will.deacon@....com>,
        Robin Murphy <robin.murphy@....com>,
        Hanjun Guo <hanjun.guo@...aro.org>,
        Sudeep Holla <sudeep.holla@....com>,
        Linux IOMMU <iommu@...ts.linux-foundation.org>,
        Robert Moore <robert.moore@...el.com>,
        Lv Zheng <lv.zheng@...el.com>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>, jcm@...hat.com,
        linux-kernel@...r.kernel.org,
        Robert Richter <robert.richter@...ium.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Sunil Goutham <sgoutham@...ium.com>,
        linux-arm-kernel@...ts.infradead.org, linux-acpi@...r.kernel.org,
        devel@...ica.org, Linu Cherian <linu.cherian@...ium.com>,
        Charles Garcia-Tobin <Charles.Garcia-Tobin@....com>,
        Rob Herring <robh@...nel.org>,
        Geetha Sowjanya <geethasowjanya.akula@...ium.com>
Subject: Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium
 ThunderX2 SMMUv3 model

On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@....com> wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian <linu.cherian@...ium.com>
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> Signed-off-by: Linu Cherian <linu.cherian@...ium.com>
>> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@...ium.com>
>> ---
>>  drivers/acpi/arm64/iort.c |   10 +++++++++-
>>  1 files changed, 9 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index c5fecf9..bba2b59 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
>>  {
>>       struct acpi_iort_smmu_v3 *smmu;
>>       int num_res = 0;
>> +     unsigned long size = SZ_128K;
>>
>>       /* Retrieve SMMUv3 specific data */
>>       smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>
>> +     /*
>> +      * Override the size, for Cavium ThunderX2 implementation
>> +      * which doesn't support the page 1 SMMU register space.
>> +      */
>> +     if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
>> +             size = SZ_64K;
>
> Nit: add a function, say arm_smmu_v3_resource_size() with the logic
> above that by default returns SZ_128K, I do not like this switch
> in the middle of this function.

I will resubmit the patch with suggested changes.


Thanks,
Geetha.
>
> Lorenzo
>
>> +
>>       res[num_res].start = smmu->base_address;
>> -     res[num_res].end = smmu->base_address + SZ_128K - 1;
>> +     res[num_res].end = smmu->base_address + size - 1;
>>       res[num_res].flags = IORESOURCE_MEM;
>>
>>       num_res++;
>> --
>> 1.7.1
>>