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Message-ID: <CACQ1gAgocEXnZ-HPHHUOs9RhyLeqPUdVm3h4q+1hBTQWOpgrfg@mail.gmail.com>
Date: Fri, 9 Jun 2017 09:40:52 +0200
From: Richard Genoud <richard.genoud@...il.com>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Alexandre Courbot <gnurou@...il.com>, Andrew Lunn <andrew@...n.ch>,
Gregory Clement <gregory.clement@...e-electrons.com>,
Jason Cooper <jason@...edaemon.net>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>,
Mark Rutland <mark.rutland@....com>,
Ralph Sennhauser <ralph.sennhauser@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Russell King <linux@...linux.org.uk>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Thierry Reding <thierry.reding@...il.com>
Subject: Re: [PATCHv2 1/2] gpio: mvebu: fix blink counter register selection
2017-06-09 9:37 GMT+02:00 Linus Walleij <linus.walleij@...aro.org>:
> On Thu, Jun 1, 2017 at 2:18 PM, Richard Genoud <richard.genoud@...il.com> wrote:
>
>> The blink counter A was always selected because 0 was forced in the
>> blink select counter register.
>> The variable 'set' was obviously there to be used as the register value,
>> selecting the B counter when id==1 and A counter when id==0.
>>
>> Tested on clearfog-pro (Marvell 88F6828)
>>
>> Fixes: 757642f9a584 ("gpio: mvebu: Add limited PWM support")
>> Reviewed-by: Gregory CLEMENT <gregory.clement@...e-electrons.com>
>> Reviewed-by: Ralph Sennhauser <ralph.sennhauser@...il.com>
>> Signed-off-by: Richard Genoud <richard.genoud@...il.com>
>
> Patch applied for fixes.
>
> It appears this will clash with patches on the development branch :(
>
> I might screw up the merges so help me check the end result
> later.
Ok, no problem !
>
> Yours,
> Linus Walleij
Thanks !
Richard.
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