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Date: Wed, 14 Jun 2017 19:00:47 +0200 From: Vlastimil Babka <vbabka@...e.cz> To: Will Deacon <will.deacon@....com>, "Aneesh Kumar K.V" <aneesh.kumar@...ux.vnet.ibm.com> Cc: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>, Andrew Morton <akpm@...ux-foundation.org>, Vineet Gupta <vgupta@...opsys.com>, Russell King <linux@...linux.org.uk>, Catalin Marinas <catalin.marinas@....com>, Ralf Baechle <ralf@...ux-mips.org>, "David S. Miller" <davem@...emloft.net>, Heiko Carstens <heiko.carstens@...ibm.com>, Martin Schwidefsky <schwidefsky@...ibm.com>, Andrea Arcangeli <aarcange@...hat.com>, linux-arch@...r.kernel.org, linux-mm@...ck.org, linux-kernel@...r.kernel.org, mark.rutland@....com Subject: Re: [HELP-NEEDED, PATCH 0/3] Do not loose dirty bit on THP pages On 06/14/2017 06:55 PM, Will Deacon wrote: >> >> May be we should relook at pmd PTE udpate interface. We really need an >> interface that can update pmd entries such that we don't clear it in >> between. IMHO, we can avoid the pmdp_invalidate() completely, if we can >> switch from a pmd PTE entry to a pointer to PTE page (pgtable_t). We also >> need this interface to avoid the madvise race fixed by > > There's a good chance I'm not following your suggestion here, but it's > probably worth me pointing out that swizzling a page table entry from a > block mapping (e.g. a huge page mapped at the PMD level) to a table entry > (e.g. a pointer to a page of PTEs) can lead to all sorts of horrible > problems on ARM, including amalgamation of TLB entries and fatal aborts. AFAIK some AMD x86_64 CPU's had the same problem and generated MCE's, and on Intel there are some restrictions when you can do that. See the large comment in __split_huge_pmd_locked(). > So we really need to go via an invalid entry, with appropriate TLB > invalidation before installing the new entry. > > Will >
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