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Message-ID: <CAOMZO5Dd243VXCYBigTcFJ2aF4prZhWYtOuw7Z86M4X6nEXB=A@mail.gmail.com>
Date: Mon, 19 Jun 2017 09:52:06 -0300
From: Fabio Estevam <festevam@...il.com>
To: Stefan Wahren <stefan.wahren@...e.com>
Cc: Oleksij Rempel <ore@...gutronix.de>,
Fabio Estevam <fabio.estevam@....com>,
Mark Rutland <mark.rutland@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Oleksij Rempel <o.rempel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Sascha Hauer <kernel@...gutronix.de>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Shawn Guo <shawnguo@...nel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v5 1/3] nvmem: dt: document SNVS LPGPR binding
Hi Stefan,
On Mon, Jun 19, 2017 at 7:58 AM, Stefan Wahren <stefan.wahren@...e.com> wrote:
> do you know how the clock "lp_ipg_clk_s" should be handled?
As per the Reference Manual there is no CCM gating bits for this clock.
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