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Message-ID: <f83cae78-4422-ce07-7a39-92ba70be8de6@i2se.com>
Date: Mon, 19 Jun 2017 16:02:29 +0200
From: Stefan Wahren <stefan.wahren@...e.com>
To: Fabio Estevam <festevam@...il.com>,
Oleksij Rempel <ore@...gutronix.de>
Cc: Fabio Estevam <fabio.estevam@....com>,
Mark Rutland <mark.rutland@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Oleksij Rempel <o.rempel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Sascha Hauer <kernel@...gutronix.de>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Shawn Guo <shawnguo@...nel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v5 1/3] nvmem: dt: document SNVS LPGPR binding
Am 19.06.2017 um 14:52 schrieb Fabio Estevam:
> Hi Stefan,
>
> On Mon, Jun 19, 2017 at 7:58 AM, Stefan Wahren <stefan.wahren@...e.com> wrote:
>
>> do you know how the clock "lp_ipg_clk_s" should be handled?
> As per the Reference Manual there is no CCM gating bits for this clock.
I was only surprised that there is no clock handling in the driver.
Sorry, about that noise.
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