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Date: Fri, 23 Jun 2017 11:06:01 +0200 From: Ingo Molnar <mingo@...nel.org> To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com> Cc: Linus Torvalds <torvalds@...ux-foundation.org>, Andrew Morton <akpm@...ux-foundation.org>, x86@...nel.org, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>, Andi Kleen <ak@...ux.intel.com>, Dave Hansen <dave.hansen@...el.com>, Andy Lutomirski <luto@...capital.net>, linux-arch@...r.kernel.org, linux-mm@...ck.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 0/5] Last bits for initial 5-level paging enabling * Kirill A. Shutemov <kirill.shutemov@...ux.intel.com> wrote: > As Ingo requested I've split and updated last two patches for my previous > patchset. > > Please review and consider applying. > > Kirill A. Shutemov (5): > x86: Enable 5-level paging support > x86/mm: Rename tasksize_32bit/64bit to task_size_32bit/64bit > x86/mpx: Do not allow MPX if we have mappings above 47-bit > x86/mm: Prepare to expose larger address space to userspace > x86/mm: Allow userspace have mapping above 47-bit Ok, looks pretty neat now. Can I apply them in this order cleanly, without breaking bisection: > x86/mm: Rename tasksize_32bit/64bit to task_size_32bit/64bit > x86/mpx: Do not allow MPX if we have mappings above 47-bit > x86/mm: Prepare to expose larger address space to userspace > x86/mm: Allow userspace have mapping above 47-bit > x86: Enable 5-level paging support ? I.e. I'd like to move the first patch last. The reason is that we should first get all quirks and assumptions fixed, all facilities implemented - and only then enable 5-level paging as a final step which produces a well working kernel. (This should also make it slightly easier to analyze any potential regressions in earlier patches.) Thanks, Ingo
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