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Message-ID: <1498318925.31581.89.camel@kernel.crashing.org>
Date:   Sat, 24 Jun 2017 10:42:05 -0500
From:   Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:     Palmer Dabbelt <palmer@...belt.com>, Arnd Bergmann <arnd@...db.de>
Cc:     linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        Olof Johansson <olof@...om.net>, albert@...ive.com,
        patches@...ups.riscv.org
Subject: Re: [PATCH 13/17] RISC-V: Add include subdirectory

On Fri, 2017-06-23 at 19:01 -0700, Palmer Dabbelt wrote:
> > > +#define mmiowb()       __asm__ __volatile__ ("fence io,io" : : : "memory");

I forgot if we already mentioned that but mmiowb is primarily intended
to order MMIO stores vs. a subsequent spin_unlock.

I'm not sure an IO only fence is sufficient here.

Note that I've never trusted drivers to get that right, it's a rather
bad abstraction to begin with, so on powerpc, instead, I just set a
per-cpu flag on every non-relaxed MMIO write and test it in spin_unlock
in order to "beef up" the barrier in there if necessary.

Cheers,
Ben.

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