linux-kernel - Re: [patches] Re: [PATCH 13/17] RISC-V: Add include subdirectory

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Message-ID: <mhng-d95a6423-75a8-4a91-bb6a-1f8765b97016@palmer-si-x1c4>
Date:   Sat, 24 Jun 2017 14:32:24 -0700 (PDT)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     benh@...nel.crashing.org
CC:     patches@...ups.riscv.org
Subject:     Re: [patches] Re: [PATCH 13/17] RISC-V: Add include subdirectory

On Sat, 24 Jun 2017 08:42:05 PDT (-0700), benh@...nel.crashing.org wrote:
> On Fri, 2017-06-23 at 19:01 -0700, Palmer Dabbelt wrote:
>> > > +#define mmiowb()       __asm__ __volatile__ ("fence io,io" : : : "memory");
>
> I forgot if we already mentioned that but mmiowb is primarily intended
> to order MMIO stores vs. a subsequent spin_unlock.
>
> I'm not sure an IO only fence is sufficient here.
>
> Note that I've never trusted drivers to get that right, it's a rather
> bad abstraction to begin with, so on powerpc, instead, I just set a
> per-cpu flag on every non-relaxed MMIO write and test it in spin_unlock
> in order to "beef up" the barrier in there if necessary.

Sorry about that -- I thought I'd included a note somewhere that the atomics
and barriers weren't ready to go yet, as we'd found a bunch of problems with
them in the first review and I needed to go through them all.  Arnd suggested
copying the PowerPC approach to mmiowb and I like that better, so we're going
to use it.

Thanks!