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Message-ID: <a7360245-5a65-7146-f295-0e90fb428173@suse.de>
Date:   Sat, 1 Jul 2017 21:56:58 +0200
From:   Andreas Färber <afaerber@...e.de>
To:     刘炜 <liuwei@...ions-semi.com>
Cc:     Arnd Bergmann <arnd@...db.de>,
        Thomas Liau <thomas.liau@...ions-semi.com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        mp-cs <mp-cs@...ions-semi.com>,
        张东风 <zhangdf@...ions-semi.com>,
        张天益 <tyzhang@...ions-semi.com>,
        96boards@...obotics.com, support@...aker.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Russell King <linux@...linux.org.uk>
Subject: Re: 答复: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

Hi David,

Am 01.07.2017 um 06:42 schrieb 刘炜:
> OWL_CPUx_ADDR is the physical address of CPUx wakeup function.
> OWL_CPUx_FLAG is a valid flag of OWL_CPUx_ADDR. 
> 
> After CPUxs are wakeuped by SEV instruction, they will check their own OWL_CPUx_FLAG register. If the register vlaue is 0x55aa, CPUx will jump to OWL_CPUx_ADDR to boot up, otherwize go to sleep by WFE.
> 
> So the pen release staff is not necessary, you can remove these code safely.

Thank you for the quick confirmation!

I have just tested a patch, and it appears to work.

Is owl_v7_invalidate_l1 necessary? mach-sunxi (that Arnd pointed to as
example) uses secondary_startup directly, without custom assembler code.

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/mach-actions/headsmp.S

> BTW: CPU2/3 must exit the power gate state before wakeup, and CPU1 is always power on and has no power gate control.

Yes, the S500 SPS was luckily documented in the manual. The power-gating
for CPU2/3 is already implemented:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/mach-actions/platsmp.c

For S900 however SPS is sadly not documented... If you know who at
Actions Semi could help there, please also take a look at:
https://github.com/96boards/documentation/issues/59

Best regards,

Andreas

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