linux-kernel - 答复: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

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Message-ID: <DC4E6E803E914F4B8AFE57F1456019F1035B7C89@srv-mail-02.actions.com.cn>
Date:   Sat, 1 Jul 2017 12:42:56 +0800
From:   刘炜 <liuwei@...ions-semi.com>
To:     Andreas Färber <afaerber@...e.de>,
        "Arnd Bergmann" <arnd@...db.de>,
        "Thomas Liau" <thomas.liau@...ions-semi.com>
Cc:     "Linux ARM" <linux-arm-kernel@...ts.infradead.org>,
        "mp-cs" <mp-cs@...ions-semi.com>,
        张东风 <zhangdf@...ions-semi.com>,
        张天益 <tyzhang@...ions-semi.com>,
        <96boards@...obotics.com>, <support@...aker.org>,
        "Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>,
        "Russell King" <linux@...linux.org.uk>
Subject: 答复: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

Hi, Andrea

OWL_CPUx_ADDR is the physical address of CPUx wakeup function.
OWL_CPUx_FLAG is a valid flag of OWL_CPUx_ADDR. 

After CPUxs are wakeuped by SEV instruction, they will check their own OWL_CPUx_FLAG register. If the register vlaue is 0x55aa, CPUx will jump to OWL_CPUx_ADDR to boot up, otherwize go to sleep by WFE.

So the pen release staff is not necessary, you can remove these code safely.

BTW: CPU2/3 must exit the power gate state before wakeup, and CPU1 is always power on and has no power gate control.

Best Regards,
David Liu

-----邮件原件-----
发件人: Andreas Färber [mailto:afaerber@...e.de] 
发送时间: 2017年6月29日 23:22
收件人: Arnd Bergmann; Thomas Liau
抄送: Linux ARM; mp-cs; 张东风; 刘炜; 张天益; 96boards@...obotics.com; support@...aker.org; Linux Kernel Mailing List; Russell King
主题: Re: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

Am 29.06.2017 um 17:07 schrieb Arnd Bergmann:
>>> +static int s500_smp_boot_secondary(unsigned int cpu, struct 
>>> +task_struct *idle) {
>>> +       unsigned long timeout;
>>> +       int ret;
>>> +
>>> +       ret = s500_wakeup_secondary(cpu);
>>> +       if (ret)
>>> +               return ret;
>>> +
>>> +       udelay(10);
>>> +
>>> +       spin_lock(&boot_lock);
>>> +
>>> +       /*
>>> +        * The secondary processor is waiting to be released from
>>> +        * the holding pen - release it, then wait for it to flag
>>> +        * that it has been released by resetting pen_release.
>>> +        */
>>> +       write_pen_release(cpu_logical_map(cpu));
>>> +       smp_send_reschedule(cpu);
>>> +
>>> +       timeout = jiffies + (1 * HZ);
>>> +       while (time_before(jiffies, timeout)) {
>>> +               if (pen_release == -1)
>>> +                       break;
>>> +       }
>>> +
>>> +       writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
>>> +       writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
>>> +
>>> +       spin_unlock(&boot_lock);
>>> +
>>> +       return pen_release != -1 ? -ENOSYS : 0; }
>>
>> This looks more complicated than necessary. Why do you need the 
>> holding pen when you have a register to start up the CPU?
>>
> 
> It seems you missed my question here. Can you please follow up, and if 
> possible send a patch to remove the pen_release logic that appears to 
> be unnecessary here?

I do not have any documentation on these registers, only the downstream code that I forward-ported here. If you tell me what you mean exactly, I can do some testing and if it still works submit a patch to simplify it.

Comments from the so far quiet Actions Semi side would help, too.

Regards,
Andreas

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