[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170726154515.GA11453@hc>
Date: Wed, 26 Jul 2017 17:45:15 +0200
From: Jan Glauber <jan.glauber@...iumnetworks.com>
To: Borislav Petkov <bp@...en8.de>
Cc: Suzuki K Poulose <Suzuki.Poulose@....com>,
Mark Rutland <mark.rutland@....com>,
Will Deacon <will.deacon@....com>,
linux-arm-kernel@...ts.infradead.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU
counters
On Wed, Jul 26, 2017 at 05:35:02PM +0200, Borislav Petkov wrote:
> On Wed, Jul 26, 2017 at 05:13:14PM +0200, Jan Glauber wrote:
> > I'm also looking for CPU implementor (MIDR), I could check for the model
> > too but I still need to detect devices based on PCI IDs as the model
> > check is not sufficient here (only multi-socket ThunderX has OCX TLK
> > devices).
>
> So what does that mean? The only way to load a PMU driver and an EDAC
> driver is the PCI ID of the memory controller? No other way?
I already tried multiple ways to load the drivers, so far with limited
success :)
The PMU/EDAC devices are all PCI devices do I need the 'struct pci_dev *'.
I'm not aware of other ways to access these devices. Please enlighten
me if I'm missing something.
--Jan
Powered by blists - more mailing lists