linux-kernel - Re: [PATCH v7 05/15] irqchip: New RISC-V PLIC Driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1501594180.29303.327.camel@linux.intel.com>
Date:   Tue, 01 Aug 2017 16:29:40 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Palmer Dabbelt <palmer@...belt.com>, peterz@...radead.org,
        tglx@...utronix.de, jason@...edaemon.net, marc.zyngier@....com,
        Arnd Bergmann <arnd@...db.de>
Cc:     yamada.masahiro@...ionext.com, mmarek@...e.com, albert@...ive.com,
        will.deacon@....com, boqun.feng@...il.com, oleg@...hat.com,
        mingo@...hat.com, daniel.lezcano@...aro.org,
        gregkh@...uxfoundation.org, jslaby@...e.com, davem@...emloft.net,
        mchehab@...nel.org, hverkuil@...all.nl, rdunlap@...radead.org,
        viro@...iv.linux.org.uk, mhiramat@...nel.org, fweisbec@...il.com,
        mcgrof@...nel.org, dledford@...hat.com, bart.vanassche@...disk.com,
        sstabellini@...nel.org, mpe@...erman.id.au,
        rmk+kernel@...linux.org.uk, paul.gortmaker@...driver.com,
        nicolas.dichtel@...nd.com, linux@...ck-us.net,
        heiko.carstens@...ibm.com, schwidefsky@...ibm.com,
        geert@...ux-m68k.org, akpm@...ux-foundation.org, jiri@...lanox.com,
        vgupta@...opsys.com, airlied@...hat.com, jk@...abs.org,
        chris@...is-wilson.co.uk, Jason@...c4.com,
        paulmck@...ux.vnet.ibm.com, ncardwell@...gle.com,
        linux-kernel@...r.kernel.org, linux-kbuild@...r.kernel.org,
        patches@...ups.riscv.org
Subject: Re: [PATCH v7 05/15] irqchip: New RISC-V PLIC Driver

On Mon, 2017-07-31 at 17:59 -0700, Palmer Dabbelt wrote:
> This patch adds a driver for the Platform Level Interrupt Controller
> (PLIC) specified as part of the RISC-V supervisor level ISA manual.
> The PLIC connocts global interrupt sources to the local interrupt
> controller on each hart.  A PLIC is present on all RISC-V systems.
> 

> +static int plic_init(struct device_node *node, struct device_node
> *parent)
> +{
> +	struct plic_data *data;
> +	struct resource resource;
> +	int i, ok = 0;
> +	int out = -1;
> +
> +	data = kzalloc(sizeof(*data), GFP_KERNEL);
> +	if (WARN_ON(!data))
> +		return -ENOMEM;
> +
> +	spin_lock_init(&data->lock);
> +
> +	data->reg = of_iomap(node, 0);
> +	if (WARN_ON(!data->reg)) {
> +		out = -EIO;
> +		goto free_data;
> +	}
> +
> +	of_property_read_u32(node, "riscv,ndev", &data->ndev);
> +	if (WARN_ON(!data->ndev)) {
> +		out = -EINVAL;
> +		goto free_reg;
> +	}
> +
> +	data->handlers = of_irq_count(node);
> +	if (WARN_ON(!data->handlers)) {
> +		out = -EINVAL;
> +		goto free_reg;
> +	}
> +
> +	data->handler =
> +		kcalloc(data->handlers, sizeof(*data->handler),
> GFP_KERNEL);
> +	if (WARN_ON(!data->handler)) {
> +		out = -ENOMEM;
> +		goto free_reg;
> +	}
> +
> +	data->domain = irq_domain_add_linear(node, data->ndev+1,
> &plic_irqdomain_ops, data);
> +	if (WARN_ON(!data->domain)) {
> +		out = -ENOMEM;
> +		goto free_handler;
> +	}
> +
> +	of_address_to_resource(node, 0, &resource);
> +	snprintf(data->name, sizeof(data->name),
> +		 "riscv,plic0,%llx", resource.start);
> +	data->chip.name = data->name;
> +	data->chip.irq_mask = plic_irq_mask;
> +	data->chip.irq_unmask = plic_irq_unmask;
> +	data->chip.irq_enable = plic_irq_enable;
> +	data->chip.irq_disable = plic_irq_disable;
> +	data->chip.irq_eoi = plic_irq_eoi;
> +
> +	for (i = 0; i < data->handlers; ++i) {
> +		struct plic_handler *handler = &data->handler[i];
> +		struct of_phandle_args parent;
> +		int parent_irq, hwirq;
> +
> +		handler->present = false;
> +
> +		if (of_irq_parse_one(node, i, &parent))
> +			continue;
> +		/* skip context holes */
> +		if (parent.args[0] == -1)
> +			continue;
> +
> +		/* skip any contexts that lead to inactive harts */
> +		if (of_device_is_compatible(parent.np, "riscv,cpu-
> intc") &&
> +		    parent.np->parent &&
> +		    riscv_of_processor_hart(parent.np->parent) < 0)
> +			continue;
> +
> +		parent_irq = irq_create_of_mapping(&parent);
> +		if (!parent_irq)
> +			continue;
> +
> +		handler->present = true;
> +		handler->contextid = i;
> +		handler->data = data;
> +		/* hwirq prio must be > this to trigger an interrupt
> */
> +		writel(0, plic_hart_threshold(data, i));
> +
> +		for (hwirq = 1; hwirq <= data->ndev; ++hwirq)
> +			plic_disable(data, i, hwirq);
> +		irq_set_chained_handler_and_data(parent_irq,
> plic_chained_handle_irq, handler);
> +		++ok;
> +	}
> +
> +	pr_info("%s: mapped %d interrupts to %d/%d handlers\n",
> +	        data->name, data->ndev, ok, data->handlers);
> +	WARN_ON(!ok);
> +	return 0;
> +
> +free_handler:
> +	kfree(data->handler);
> +free_reg:
> +	iounmap(data->reg);
> +free_data:
> +	kfree(data);
> +	return out;
> +}

Something warns me on about this function.

> +
> +IRQCHIP_DECLARE(plic0, "riscv,plic0", plic_init);

-- 
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Intel Finland Oy