linux-kernel - Re: [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT

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Message-ID: <CAAhV-H5r8Mv8YjBBBooXc4zmaZkNq9MHBpxtTZ4V-YozC8w4xQ@mail.gmail.com>
Date:   Mon, 21 Aug 2017 10:24:39 +0800
From:   Huacai Chen <chenhc@...ote.com>
To:     Ben Hutchings <ben@...adent.org.uk>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        stable <stable@...r.kernel.org>, akpm@...ux-foundation.org,
        Fuxin Zhang <zhangfx@...ote.com>,
        "Steven J . Hill" <Steven.Hill@...iumnetworks.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Zhangjin Wu <wuzhangjin@...il.com>,
        Linux MIPS Mailing List <linux-mips@...ux-mips.org>,
        John Crispin <john@...ozen.org>
Subject: Re: [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

3.16 doesn't need this, because 3.16 doesn't support Loongson-3 R2/R3.

Huacai

On Fri, Aug 18, 2017 at 9:13 PM, Ben Hutchings <ben@...adent.org.uk> wrote:
> 3.16.47-rc1 review patch.  If anyone has any objections, please let me know.
>
> ------------------
>
> From: Huacai Chen <chenhc@...ote.com>
>
> commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.
>
> Some newer Loongson-3 have 64 bytes cache lines, so select
> MIPS_L1_CACHE_SHIFT_6.
>
> Signed-off-by: Huacai Chen <chenhc@...ote.com>
> Cc: John Crispin <john@...ozen.org>
> Cc: Steven J . Hill <Steven.Hill@...iumnetworks.com>
> Cc: Fuxin Zhang <zhangfx@...ote.com>
> Cc: Zhangjin Wu <wuzhangjin@...il.com>
> Cc: linux-mips@...ux-mips.org
> Patchwork: https://patchwork.linux-mips.org/patch/15755/
> Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
> [bwh: Backported to 3.16: adjust context]
> Signed-off-by: Ben Hutchings <ben@...adent.org.uk>
> ---
>  arch/mips/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1193,6 +1193,7 @@ config CPU_LOONGSON3
>         select CPU_SUPPORTS_HUGEPAGES
>         select WEAK_ORDERING
>         select WEAK_REORDERING_BEYOND_LLSC
> +       select MIPS_L1_CACHE_SHIFT_6
>         help
>                 The Loongson 3 processor implements the MIPS64R2 instruction
>                 set with many extensions.
>
>