linux-kernel - Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA

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Message-ID: <tencent_31D6F9A339CED0D66B83CBD8@qq.com>
Date:   Thu, 14 Sep 2017 09:13:47 +0800
From:   "陈华才" <chenhc@...ote.com>
To:     "Andrew Morton" <akpm@...ux-foundation.org>
Cc:     "Fuxin Zhang" <zhangfx@...ote.com>,
        "linux-mm" <linux-mm@...ck.org>,
        "linux-kernel" <linux-kernel@...r.kernel.org>,
        "stable" <stable@...r.kernel.org>
Subject: Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode

Hi, Andrew,

It will cause data corruption, at least on MIPS:
step 1, dma_map_single
step 2, cache_invalidate (no writeback)
step 3, dma_from_device
step 4, dma_unmap_single
If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) may cause data lost.
 
Huacai
 
------------------ Original ------------------
From:  "Andrew Morton"<akpm@...ux-foundation.org>;
Date:  Thu, Sep 14, 2017 05:52 AM
To:  "Huacai Chen"<chenhc@...ote.com>; 
Cc:  "Fuxin Zhang"<zhangfx@...ote.com>; "linux-mm"<linux-mm@...ck.org>; "linux-kernel"<linux-kernel@...r.kernel.org>; "stable"<stable@...r.kernel.org>; 
Subject:  Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode

 
On Wed, 13 Sep 2017 17:20:51 +0800 Huacai Chen <chenhc@...ote.com> wrote:

> In non-coherent DMA mode, kernel uses cache flushing operations to
> maintain I/O coherency, so the dmapool objects should be aligned to
> ARCH_DMA_MINALIGN.

What are the user-visible effects of this bug?