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Date:   Mon, 18 Sep 2017 15:03:30 +0800
From:   "陈华才" <>
To:     "Christoph Hellwig" <>
Cc:     "James E . J . Bottomley" 
        "Martin K . Petersen" 
        "Andrew Morton" <>,
        "Fuxin Zhang" <>,
        "linux-scsi" <>,
        "linux-kernel" <>,
        "stable" <>
Subject: Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode

Hi, Christoph,

I don't think dma_get_cache_alignment is the "absolute minimum alignment" in all cases. At least on MIPS/Loongson, if we use I/O coherent mode (Cached DMA mode), align block queue to 4Bytes is enough. If we align block queue  to dma_get_cache_alignment in I/O coherent mode, there are peformance lost because we cannot use zero-copy in most cases (user buffers are usually not aligned).

------------------ Original ------------------
From:  "Christoph Hellwig"<>;
Date:  Mon, Sep 18, 2017 01:20 PM
To:  "Huacai Chen"<>;
Cc:  "James E . J . Bottomley"<>; "Martin K . Petersen"<>; "Andrew Morton"<>; "Fuxin Zhang"<>; "linux-scsi"<>; "linux-kernel"<>; "stable"<>;
Subject:  Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode
Please send all patches in the series to the same to and cc lists.

On Mon, Sep 18, 2017 at 12:22:54PM +0800, Huacai Chen wrote:
> In non-coherent DMA mode, kernel uses cache flushing operations to
> maintain I/O coherency, so scsi's block queue should be aligned to
> ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least
> on MIPS:
>         Step 1, dma_map_single
>         Step 2, cache_invalidate (no writeback)
>         Step 3, dma_from_device
>         Step 4, dma_unmap_single
> If a DMA buffer and a kernel structure share a same cache line, and if
> the kernel structure has dirty data, cache_invalidate (no writeback)
> will cause data lost.

And as said before we must _always_ align to dma_get_cache_alignment.
This is even documented in Documentation/DMA-API.txt:

------------------------------ snip ------------------------------


Returns the processor cache alignment.  This is the absolute minimum
alignment *and* width that you must observe when either mapping
memory or doing partial flushes.

------------------------------ snip ------------------------------

> +	if (device_is_coherent(dev))
> +	blk_queue_dma_alignment(q, 0x04 - 1);
> +	else
> +	blk_queue_dma_alignment(q, dma_get_cache_alignment() - 1);

So as said before this should become something like:

blk_queue_dma_alignment(q, max(0x04, dma_get_cache_alignment()) - 1);

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