linux-kernel - Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA

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Message-ID: <20170918155029.GB16672@infradead.org>
Date:   Mon, 18 Sep 2017 08:50:29 -0700
From:   Christoph Hellwig <hch@...radead.org>
To:     陈华才 <chenhc@...ote.com>
Cc:     Christoph Hellwig <hch@...radead.org>,
        "James E . J . Bottomley" <jejb@...ux.vnet.ibm.com>,
        "Martin K . Petersen" <martin.petersen@...cle.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Fuxin Zhang <zhangfx@...ote.com>,
        linux-scsi <linux-scsi@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        stable <stable@...r.kernel.org>
Subject: Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN
 innon-coherent DMA mode

On Mon, Sep 18, 2017 at 03:03:30PM +0800, 陈华才 wrote:
> I don't think dma_get_cache_alignment is the "absolute minimum alignment" in all cases. At least on MIPS/Loongson, if we use I/O coherent mode (Cached DMA mode), align block queue to 4Bytes is enough. If we align block queue  to dma_get_cache_alignment in I/O coherent mode, there are peformance lost because we cannot use zero-copy in most cases (user buffers are usually not aligned).

If you systems is I/O coherent it should report 1 ARCH_DMA_MINALIGN /
dma_get_cache_alignment().

Note that many drivers only support 512 byte aligned mappings for
block I/O and they've done pretty fine so far.