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Date:   Wed, 4 Oct 2017 11:02:32 -0400
From:   Steven Rostedt <rostedt@...dmis.org>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>, pmladek@...e.com,
        sergey.senozhatsky@...il.com, linux-kernel@...r.kernel.org,
        mingo@...nel.org, tglx@...utronix.de
Subject: Re: [PATCH 3/3] early_printk: Add simple serialization to
 early_vprintk()

On Wed, 4 Oct 2017 16:52:47 +0200
Peter Zijlstra <peterz@...radead.org> wrote:

> On Wed, Oct 04, 2017 at 10:43:54AM -0400, Steven Rostedt wrote:
> > 
> > My question is not about ordering, but about coherency. Can you have
> > one CPU read a variable that goes into cache, and keep using the cached
> > variable every time the program asks to read it, instead of going out
> > to memory.  
> 
> No, not on a coherent system.

In this case.

Reviewed-by: Steven Rostedt (VMware) <rostedt@...dmis.org>

-- Steve

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