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Date:   Sat, 7 Oct 2017 08:30:57 +0800
From:   Wanpeng Li <kernellwp@...il.com>
To:     Radim Krčmář <rkrcmar@...hat.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        kvm <kvm@...r.kernel.org>, Paolo Bonzini <pbonzini@...hat.com>
Subject: Re: [PATCH 3/3] KVM: x86: thoroughly disarm LAPIC timer around TSC
 deadline switch

2017-10-07 1:25 GMT+08:00 Radim Krčmář <rkrcmar@...hat.com>:
> Our routines look at tscdeadline and period when deciding state of a
> timer.  The timer is disarmed when switching between TSC deadline and
> other modes, so we should set everything to disarmed state.
>
> Signed-off-by: Radim Krčmář <rkrcmar@...hat.com>

Reviewed-by: Wanpeng Li <wanpeng.li@...mail.com>

> ---
>  arch/x86/kvm/lapic.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 96ade848ae0b..a778f1ae2927 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1330,8 +1330,10 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
>         if (apic->lapic_timer.timer_mode != timer_mode) {
>                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
>                                 APIC_LVT_TIMER_TSCDEADLINE)) {
> -                       kvm_lapic_set_reg(apic, APIC_TMICT, 0);
>                         hrtimer_cancel(&apic->lapic_timer.timer);
> +                       kvm_lapic_set_reg(apic, APIC_TMICT, 0);
> +                       apic->lapic_timer.period = 0;
> +                       apic->lapic_timer.tscdeadline = 0;
>                 }
>                 apic->lapic_timer.timer_mode = timer_mode;
>                 limit_periodic_timer_frequency(apic);
> --
> 2.14.2
>

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