linux-kernel - RE: [PATCH] EDAC, sb_edac: mark expected switch fall-through

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Date:   Mon, 16 Oct 2017 03:00:53 +0000
From:   "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>
To:     "Gustavo A. R. Silva" <garsilva@...eddedor.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Borislav Petkov <bp@...en8.de>
CC:     "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] EDAC, sb_edac: mark expected switch fall-through

Hi Silva,

    The actual intention of the code is NOT to fall through, though current code can work correctly.
    Thanks for this finding. If you don't mind, I'll submit a fix patch for it with the tag 'Reported-by:' by you.

Thanks!
- Qiuxu

> From: linux-edac-owner@...r.kernel.org [mailto:linux-edac-
> owner@...r.kernel.org] On Behalf Of Gustavo A. R. Silva
> Sent: Saturday, October 14, 2017 4:28 AM
> To: Mauro Carvalho Chehab <mchehab@...nel.org>; Borislav Petkov
> <bp@...en8.de>
> Cc: linux-edac@...r.kernel.org; linux-kernel@...r.kernel.org; Gustavo A. R.
> Silva <garsilva@...eddedor.com>
> Subject: [PATCH] EDAC, sb_edac: mark expected switch fall-through
> 
> In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we
> are expecting to fall through.
> 
> Signed-off-by: Gustavo A. R. Silva <garsilva@...eddedor.com>
> ---
> This code was tested by compilation only (GCC 7.2.0 was used).
> Please, verify if the actual intention of the code is to fall through.
> 
>  drivers/edac/sb_edac.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index
> 72b98a0..b50d714 100644
> --- a/drivers/edac/sb_edac.c
> +++ b/drivers/edac/sb_edac.c
> @@ -2485,6 +2485,7 @@ static int ibridge_mci_bind_devs(struct mem_ctl_info
> *mci,
>  		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
>  		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
>  			pvt->pci_ta = pdev;
> +			/* fall through */
>  		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
>  		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS: