linux-kernel - [tip:x86/timers] x86/tsc: Add option that TSC on Socket 0 being non-zero is valid

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Message-ID: <tip-341102c3ef29c33611586072363cf9982a8bdb77@git.kernel.org>
Date:   Mon, 16 Oct 2017 14:15:55 -0700
From:   "tip-bot for mike.travis@....com" <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mingo@...nel.org, mike.travis@....com, tglx@...utronix.de,
        bin.gao@...ux.intel.com, peterz@...radead.org,
        andrew.abanman@....com, andrew.banman@....com, hpa@...or.com,
        russ.anderson@....com, linux-kernel@...r.kernel.org,
        dimitri.sivanich@....com, prarit@...hat.com
Subject: [tip:x86/timers] x86/tsc: Add option that TSC on Socket 0 being
 non-zero is valid

Commit-ID:  341102c3ef29c33611586072363cf9982a8bdb77
Gitweb:     https://git.kernel.org/tip/341102c3ef29c33611586072363cf9982a8bdb77
Author:     mike.travis@....com <mike.travis@....com>
AuthorDate: Thu, 12 Oct 2017 11:32:02 -0500
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 16 Oct 2017 22:50:36 +0200

x86/tsc: Add option that TSC on Socket 0 being non-zero is valid

Add a flag to indicate and process that TSC counters are on chassis
that reset at different times during system startup.  Therefore which
TSC ADJUST values should be zero is not predictable.

Signed-off-by: Mike Travis <mike.travis@....com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@....com>
Reviewed-by: Russ Anderson <russ.anderson@....com>
Reviewed-by: Andrew Banman <andrew.abanman@....com>
Reviewed-by: Peter Zijlstra <peterz@...radead.org>
Cc: Prarit Bhargava <prarit@...hat.com>
Cc: Andrew Banman <andrew.banman@....com>
Cc: Bin Gao <bin.gao@...ux.intel.com>
Link: https://lkml.kernel.org/r/20171012163201.944370012@stormcage.americas.sgi.com

---
 arch/x86/include/asm/tsc.h |  2 ++
 arch/x86/kernel/tsc_sync.c | 39 +++++++++++++++++++++++++++++++++++----
 2 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index d0509c7..79125f3 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -36,11 +36,13 @@ extern void tsc_init(void);
 extern void mark_tsc_unstable(char *reason);
 extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
+extern void mark_tsc_async_resets(char *reason);
 extern unsigned long native_calibrate_cpu(void);
 extern unsigned long native_calibrate_tsc(void);
 extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
 
 extern int tsc_clocksource_reliable;
+extern bool tsc_async_resets;
 
 /*
  * Boot-time check whether the TSCs are synchronized across
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 7842371..3873dcd 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -30,6 +30,20 @@ struct tsc_adjust {
 
 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
 
+/*
+ * TSC's on different sockets may be reset asynchronously.
+ * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
+ */
+bool __read_mostly tsc_async_resets;
+
+void mark_tsc_async_resets(char *reason)
+{
+	if (tsc_async_resets)
+		return;
+	tsc_async_resets = true;
+	pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
+}
+
 void tsc_verify_tsc_adjust(bool resume)
 {
 	struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
@@ -71,12 +85,22 @@ static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
 	 * non zero. We don't do that on non boot cpus because physical
 	 * hotplug should have set the ADJUST register to a value > 0 so
 	 * the TSC is in sync with the already running cpus.
+	 *
+	 * Also don't force the ADJUST value to zero if that is a valid value
+	 * for socket 0 as determined by the system arch.  This is required
+	 * when multiple sockets are reset asynchronously with each other
+	 * and socket 0 may not have an TSC ADJUST value of 0.
 	 */
 	if (bootcpu && bootval != 0) {
-		pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,
-			bootval);
-		wrmsrl(MSR_IA32_TSC_ADJUST, 0);
-		bootval = 0;
+		if (likely(!tsc_async_resets)) {
+			pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
+				cpu, bootval);
+			wrmsrl(MSR_IA32_TSC_ADJUST, 0);
+			bootval = 0;
+		} else {
+			pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
+				cpu, bootval);
+		}
 	}
 	cur->adjusted = bootval;
 }
@@ -118,6 +142,13 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
 	cur->warned = false;
 
 	/*
+	 * If a non-zero TSC value for socket 0 may be valid then the default
+	 * adjusted value cannot assumed to be zero either.
+	 */
+	if (tsc_async_resets)
+		cur->adjusted = bootval;
+
+	/*
 	 * Check whether this CPU is the first in a package to come up. In
 	 * this case do not check the boot value against another package
 	 * because the new package might have been physically hotplugged,