linux-kernel - [tip:x86/timers] x86/tsc: Provide a means to disable TSC ART

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Message-ID: <tip-6c66350d0a482892793b888b07c1177fc6d4b344@git.kernel.org>
Date:   Mon, 16 Oct 2017 14:17:10 -0700
From:   "tip-bot for mike.travis@....com" <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, russ.anderson@....com,
        mike.travis@....com, peterz@...radead.org, prarit@...hat.com,
        hpa@...or.com, dimitri.sivanich@....com, mingo@...nel.org,
        andrew.banman@....com, bin.gao@...ux.intel.com, tglx@...utronix.de
Subject: [tip:x86/timers] x86/tsc: Provide a means to disable TSC ART

Commit-ID:  6c66350d0a482892793b888b07c1177fc6d4b344
Gitweb:     https://git.kernel.org/tip/6c66350d0a482892793b888b07c1177fc6d4b344
Author:     mike.travis@....com <mike.travis@....com>
AuthorDate: Thu, 12 Oct 2017 11:32:05 -0500
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 16 Oct 2017 22:50:37 +0200

x86/tsc: Provide a means to disable TSC ART

On systems where multiple chassis are reset asynchronously, and thus
the TSC counters are started asynchronously, the offset needed to
convert to TSC to ART would be different.  Disable ART in that case
and rely on the TSC counters to supply the accurate time.

Signed-off-by: Mike Travis <mike.travis@....com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Prarit Bhargava <prarit@...hat.com>
Cc: Dimitri Sivanich <dimitri.sivanich@....com>
Cc: Russ Anderson <russ.anderson@....com>
Cc: Andrew Banman <andrew.banman@....com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Bin Gao <bin.gao@...ux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.289397994@stormcage.americas.sgi.com

---
 arch/x86/kernel/tsc.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 896dbe3..f1326c0 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -962,10 +962,14 @@ static void detect_art(void)
 	if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
 		return;
 
-	/* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
+	/*
+	 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
+	 * and the TSC counter resets must not occur asynchronously.
+	 */
 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
 	    !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
-	    !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
+	    !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
+	    tsc_async_resets)
 		return;
 
 	cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,