linux-kernel - Re: [PATCH v2] KVM: X86: #GP when guest attempts to write MCi

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Message-ID: <CALMp9eQFEVLwV8ZW3HtO__rOfEd1Qs-ZJvqwT-5SAmU2zRonvA@mail.gmail.com>
Date:   Thu, 19 Oct 2017 11:09:12 -0700
From:   Jim Mattson <jmattson@...gle.com>
To:     Wanpeng Li <kernellwp@...il.com>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        kvm list <kvm@...r.kernel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH v2] KVM: X86: #GP when guest attempts to write MCi_STATUS
 register w/o 0

"(offset & 0x3) == 1" seems like an obfuscated way of writing the
predicate, is_mci_status_msr(msr). But other than that, this change
looks fine to me.

I'm a little more concerned about the code above. At the very least,
it needs to let the host set an arbitrary value for save/restore to
work.

Reviewed-by: Jim Mattson <jmattson@...gle.com>

On Thu, Oct 19, 2017 at 6:47 AM, Wanpeng Li <kernellwp@...il.com> wrote:
> From: Wanpeng Li <wanpeng.li@...mail.com>
>
> Both Intel SDM and AMD APM mentioned that MCi_STATUS, when the register is
> implemented, this register can be cleared by explicitly writing 0s to this
> register. Writing 1s to this register will cause a general-protection
> exception.
>
> The mce is emulated in qemu, so just the guest attempts to write 1 to this
> register should cause a #GP, this patch does it.
>
> Cc: Paolo Bonzini <pbonzini@...hat.com>
> Cc: Radim Krčmář <rkrcmar@...hat.com>
> Cc: Jim Mattson <jmattson@...gle.com>
> Signed-off-by: Wanpeng Li <wanpeng.li@...mail.com>
> ---
> v1 -> v2:
>  * just #GP MCi_STATUS
>
>  arch/x86/kvm/x86.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 5669af0..a8680ea 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2006,10 +2006,12 @@ static void kvmclock_sync_fn(struct work_struct *work)
>                                         KVMCLOCK_SYNC_PERIOD);
>  }
>
> -static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
> +static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  {
>         u64 mcg_cap = vcpu->arch.mcg_cap;
>         unsigned bank_num = mcg_cap & 0xff;
> +       u32 msr = msr_info->index;
> +       u64 data = msr_info->data;
>
>         switch (msr) {
>         case MSR_IA32_MCG_STATUS:
> @@ -2034,6 +2036,9 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
>                         if ((offset & 0x3) == 0 &&
>                             data != 0 && (data | (1 << 10)) != ~(u64)0)
>                                 return -1;
> +                       if (!msr_info->host_initiated &&
> +                               (offset & 0x3) == 1 && data != 0)
> +                               return -1;
>                         vcpu->arch.mce_banks[offset] = data;
>                         break;
>                 }
> @@ -2283,7 +2288,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>         case MSR_IA32_MCG_CTL:
>         case MSR_IA32_MCG_STATUS:
>         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
> -               return set_msr_mce(vcpu, msr, data);
> +               return set_msr_mce(vcpu, msr_info);
>
>         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
>         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
> --
> 2.7.4
>