| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <tip-4efea85fb56fa1691b79af1eea4c1425660cf4e3@git.kernel.org>
Date: Wed, 1 Nov 2017 14:01:16 -0700
From: tip-bot for Ricardo Neri <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: akpm@...ux-foundation.org, keescook@...omium.org,
linux-kernel@...r.kernel.org, thgarnie@...gle.com,
adrian.hunter@...el.com, ravi.v.shankar@...el.com,
dave.hansen@...ux.intel.com, bp@...e.de, adam.buchbinder@...il.com,
pbonzini@...hat.com, brgerst@...il.com, hpa@...or.com,
corbet@....net, peterz@...radead.org, mingo@...nel.org,
colin.king@...onical.com, paul.gortmaker@...driver.com,
mst@...hat.com, acme@...hat.com,
ricardo.neri-calderon@...ux.intel.com, ray.huang@....com,
tglx@...utronix.de, shuah@...nel.org, dvyukov@...gle.com,
cmetcalf@...lanox.com, mhiramat@...nel.org, slaoub@...il.com,
jslaby@...e.cz, luto@...nel.org, vbabka@...e.cz,
qiaowei.ren@...el.com, lstoakes@...il.com
Subject: [tip:x86/mpx] x86/insn-eval: Add function to get default params of
code segment
Commit-ID: 4efea85fb56fa1691b79af1eea4c1425660cf4e3
Gitweb: https://git.kernel.org/tip/4efea85fb56fa1691b79af1eea4c1425660cf4e3
Author: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
AuthorDate: Fri, 27 Oct 2017 13:25:43 -0700
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitDate: Wed, 1 Nov 2017 21:50:12 +0100
x86/insn-eval: Add function to get default params of code segment
Obtain the default values of the address and operand sizes as specified in
the D and L bits of the the segment descriptor selected by the register
CS. The function can be used for both protected and long modes.
For virtual-8086 mode, the default address and operand sizes are always 2
bytes.
The returned parameters are encoded in a signed 8-bit data type. Auxiliar
macros are provided to encode and decode such values.
Improvements-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Borislav Petkov <bp@...e.de>
Cc: "Michael S. Tsirkin" <mst@...hat.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: ricardo.neri@...el.com
Cc: Adrian Hunter <adrian.hunter@...el.com>
Cc: Paul Gortmaker <paul.gortmaker@...driver.com>
Cc: Huang Rui <ray.huang@....com>
Cc: Qiaowei Ren <qiaowei.ren@...el.com>
Cc: Shuah Khan <shuah@...nel.org>
Cc: Kees Cook <keescook@...omium.org>
Cc: Jonathan Corbet <corbet@....net>
Cc: Jiri Slaby <jslaby@...e.cz>
Cc: Dmitry Vyukov <dvyukov@...gle.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@...el.com>
Cc: Chris Metcalf <cmetcalf@...lanox.com>
Cc: Brian Gerst <brgerst@...il.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Colin Ian King <colin.king@...onical.com>
Cc: Chen Yucong <slaoub@...il.com>
Cc: Adam Buchbinder <adam.buchbinder@...il.com>
Cc: Vlastimil Babka <vbabka@...e.cz>
Cc: Lorenzo Stoakes <lstoakes@...il.com>
Cc: Masami Hiramatsu <mhiramat@...nel.org>
Cc: Paolo Bonzini <pbonzini@...hat.com>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Cc: Thomas Garnier <thgarnie@...gle.com>
Link: https://lkml.kernel.org/r/1509135945-13762-17-git-send-email-ricardo.neri-calderon@linux.intel.com
---
arch/x86/include/asm/insn-eval.h | 5 ++++
arch/x86/lib/insn-eval.c | 64 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index 25d6e44..e1d3b4c 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -11,8 +11,13 @@
#include <linux/err.h>
#include <asm/ptrace.h>
+#define INSN_CODE_SEG_ADDR_SZ(params) ((params >> 4) & 0xf)
+#define INSN_CODE_SEG_OPND_SZ(params) (params & 0xf)
+#define INSN_CODE_SEG_PARAMS(oper_sz, addr_sz) (oper_sz | (addr_sz << 4))
+
void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs);
int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs);
unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx);
+char insn_get_code_seg_params(struct pt_regs *regs);
#endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 89d5c89..01e36bd 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -640,6 +640,70 @@ static unsigned long get_seg_limit(struct pt_regs *regs, int seg_reg_idx)
}
/**
+ * insn_get_code_seg_params() - Obtain code segment parameters
+ * @regs: Structure with register values as seen when entering kernel mode
+ *
+ * Obtain address and operand sizes of the code segment. It is obtained from the
+ * selector contained in the CS register in regs. In protected mode, the default
+ * address is determined by inspecting the L and D bits of the segment
+ * descriptor. In virtual-8086 mode, the default is always two bytes for both
+ * address and operand sizes.
+ *
+ * Returns:
+ *
+ * A signed 8-bit value containing the default parameters on success.
+ *
+ * -EINVAL on error.
+ */
+char insn_get_code_seg_params(struct pt_regs *regs)
+{
+ struct desc_struct *desc;
+ short sel;
+
+ if (v8086_mode(regs))
+ /* Address and operand size are both 16-bit. */
+ return INSN_CODE_SEG_PARAMS(2, 2);
+
+ sel = get_segment_selector(regs, INAT_SEG_REG_CS);
+ if (sel < 0)
+ return sel;
+
+ desc = get_desc(sel);
+ if (!desc)
+ return -EINVAL;
+
+ /*
+ * The most significant byte of the Type field of the segment descriptor
+ * determines whether a segment contains data or code. If this is a data
+ * segment, return error.
+ */
+ if (!(desc->type & BIT(3)))
+ return -EINVAL;
+
+ switch ((desc->l << 1) | desc->d) {
+ case 0: /*
+ * Legacy mode. CS.L=0, CS.D=0. Address and operand size are
+ * both 16-bit.
+ */
+ return INSN_CODE_SEG_PARAMS(2, 2);
+ case 1: /*
+ * Legacy mode. CS.L=0, CS.D=1. Address and operand size are
+ * both 32-bit.
+ */
+ return INSN_CODE_SEG_PARAMS(4, 4);
+ case 2: /*
+ * IA-32e 64-bit mode. CS.L=1, CS.D=0. Address size is 64-bit;
+ * operand size is 32-bit.
+ */
+ return INSN_CODE_SEG_PARAMS(4, 8);
+ case 3: /* Invalid setting. CS.L=1, CS.D=1 */
+ /* fall through */
+ default:
+ return -EINVAL;
+ }
+}
+
+/**
* insn_get_modrm_rm_off() - Obtain register in r/m part of the ModRM byte
* @insn: Instruction containing the ModRM byte
* @regs: Register values as seen when entering kernel mode
Powered by blists - more mailing lists