lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 2 Nov 2017 09:06:36 -0700
From:   David Daney <ddaney@...iumnetworks.com>
To:     Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>
Cc:     David Daney <david.daney@...ium.com>, linux-mips@...ux-mips.org,
        ralf@...ux-mips.org, James Hogan <james.hogan@...s.com>,
        netdev@...r.kernel.org, "David S. Miller" <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-kernel@...r.kernel.org,
        "Steven J. Hill" <steven.hill@...ium.com>,
        devicetree@...r.kernel.org, Carlos Munoz <cmunoz@...ium.com>
Subject: Re: [PATCH 1/7] dt-bindings: Add Cavium Octeon Common Ethernet
 Interface.

On 11/02/2017 05:47 AM, Andrew Lunn wrote:
> On Wed, Nov 01, 2017 at 06:09:17PM -0700, Florian Fainelli wrote:
>> On 11/01/2017 05:36 PM, David Daney wrote:
>>> From: Carlos Munoz <cmunoz@...ium.com>
>>>
>>> Add bindings for Common Ethernet Interface (BGX) block.
>>>
>>> Signed-off-by: Carlos Munoz <cmunoz@...ium.com>
>>> Signed-off-by: Steven J. Hill <Steven.Hill@...ium.com>
>>> Signed-off-by: David Daney <david.daney@...ium.com>
>>> ---
>> [snip]
>>> +Properties:
>>> +
>>> +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
>>> +
>>> +- reg: The index of the interface within the BGX block.
>>> +
>>> +- local-mac-address: Mac address for the interface.
>>> +
>>> +- phy-handle: phandle to the phy node connected to the interface.
>>> +
>>> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
>>> +  Needed by the Micrel PHY.
>>
>> Is not that implied by an appropriate "phy-mode" property already?
> 
> Hi Florian
> 
> Looking at the driver patch, phy-mode is not used at
> all. of_phy_connect() passes a hard coded SGMII value!
> 
> David, you need to fix this.
> 

Yes, I think you are correct.

Thanks for reviewing this,

David Daney

Powered by blists - more mailing lists