lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 09 Nov 2017 13:54:27 -0800 (PST) From: Palmer Dabbelt <palmer@...ive.com> To: luc.vanoostenryck@...il.com CC: albert@...ive.com, patches@...ups.riscv.org, linux-kernel@...r.kernel.org Subject: Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse On Thu, 09 Nov 2017 13:46:50 PST (-0800), luc.vanoostenryck@...il.com wrote: > On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt <palmer@...ive.com> wrote: >> On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@...il.com wrote: >>> The goal of these two patches is to ass endianness and machine >>> size info to sparse so that sparse can emit correct diagnostics >>> even when the endianness and machine size doesn't correspond to >>> sparse's defaults. >>> >>> Luc Van Oostenryck (2): >>> riscv: pass endianness info to sparse >>> riscv: pass machine size to sparse >>> >>> arch/riscv/Makefile | 4 ++++ >>> 1 file changed, 4 insertions(+) >> >> Thanks! I'll take these into the RISC-V tree. > > Well, better to hold one because someone has asked > to treat the problem in a generic way (the same problem exist > on other archs) and I certainly think it's indeed better. > > I'll sent a newer patch in a day or two. OK, no problem. I'm re-organizing our big list of outstanding patches (in addition the reviewed ones I'll be sending up), so I'll just leave this on a staging branch. Thanks!
Powered by blists - more mailing lists