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Message-ID: <20171116064715.GC24950@dragon>
Date: Thu, 16 Nov 2017 14:47:16 +0800
From: Shawn Guo <shawn.guo@...aro.org>
To: Jiancheng Xue <xuejiancheng@...ilicon.com>
Cc: hermit.wangheming@...ilicon.com, sboyd@...eaurora.org,
mturquette@...libre.com, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, project-aspen-dev@...aro.org,
tianshuliang <tianshuliang@...ilicon.com>
Subject: Re: [project-aspen-dev] Re: [PATCH 1/3] clk: hisilicon: add hisi
phase clock support
On Thu, Nov 16, 2017 at 11:40:18AM +0800, Jiancheng Xue wrote:
> >> +struct clk_hisi_phase {
> >> + struct clk_hw hw;
> >> + void __iomem *reg;
> >> + u32 *phase_values;
> >> + u32 *phase_regs;
> >> + u8 phase_num;
> >
> > I do not think this value-reg table is necessary, as the register value
> > maps to phase degree in a way that is easy for programming, i.e. degree
> > increases 45 with register value increases one.
> >
> We expected that this interface could be more generic. That means it can
> be also used in other maps instances.
Okay, if you think there will be some case using different programming
model, I'm fine with it.
Shawn
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