linux-kernel - Re: [PATCH 1/2 v2] dmaengine: rcar-dmac: ensure CHCR DE bit is actually 0 after clear

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Message-ID: <1874044.cuZmJqfgp6@avalon>
Date:   Tue, 21 Nov 2017 10:16:58 +0200
From:   Laurent Pinchart <laurent.pinchart@...asonboard.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        Dan Williams <dan.j.williams@...el.com>,
        Vinod Koul <vinod.koul@...el.com>,
        Niklas Söderlund 
        <niklas.soderlund+renesas@...natech.se>, dmaengine@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@...esas.com>
Subject: Re: [PATCH 1/2 v2] dmaengine: rcar-dmac: ensure CHCR DE bit is actually 0 after clear

On Friday, 17 November 2017 10:41:05 EET Geert Uytterhoeven wrote:
> On Fri, Nov 17, 2017 at 1:10 AM, Kuninori Morimoto wrote:
> >>> +static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
> >>> +{
> >>> +       u32 chcr;
> >>> +       int i;
> >> 
> >> unsigned int
> >> 
> >>> +
> >>> +       /*
> >>> +        * Ensure that the setting of the DE bit is actually 0 after
> >>> +        * clearing it.
> >>> +        */
> >>> +       for (i = 0; i < 1024; i++) {
> >>> +               chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
> >>> +               if (!(chcr & RCAR_DMACHCR_DE))
> >>> +                       return;
> >>> +               udelay(1);
> >>> +       }
> >> 
> >> What's a typical number of loops needed before DE is really cleared?
> > 
> > It case by case, but I don't want to use while(1) loop
> 
> I understand that, and I agree wholeheartedly with limiting the number
> of cycles.

So do I, but I'd still like to know what the typical values are :-)

-- 
Regards,

Laurent Pinchart