linux-kernel - Re: [PATCH 1/2 v2] dmaengine: rcar-dmac: ensure CHCR DE bit is actually 0 after clear

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Message-ID: <878tez9ju5.wl%kuninori.morimoto.gx@renesas.com>
Date:   Wed, 22 Nov 2017 01:44:05 +0000
From:   Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
To:     Laurent Pinchart <laurent.pinchart@...asonboard.com>
Cc:     Geert Uytterhoeven <geert@...ux-m68k.org>,
        Dan Williams <dan.j.williams@...el.com>,
        Vinod Koul <vinod.koul@...el.com>,
        Niklas Söderlund 
        <niklas.soderlund+renesas@...natech.se>, dmaengine@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@...esas.com>
Subject: Re: [PATCH 1/2 v2] dmaengine: rcar-dmac: ensure CHCR DE bit is actually 0 after clear


Hi Laurent

> > >>> +static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
> > >>> +{
> > >>> +       u32 chcr;
> > >>> +       int i;
> > >> 
> > >> unsigned int
> > >> 
> > >>> +
> > >>> +       /*
> > >>> +        * Ensure that the setting of the DE bit is actually 0 after
> > >>> +        * clearing it.
> > >>> +        */
> > >>> +       for (i = 0; i < 1024; i++) {
> > >>> +               chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
> > >>> +               if (!(chcr & RCAR_DMACHCR_DE))
> > >>> +                       return;
> > >>> +               udelay(1);
> > >>> +       }
> > >> 
> > >> What's a typical number of loops needed before DE is really cleared?
> > > 
> > > It case by case, but I don't want to use while(1) loop
> > 
> > I understand that, and I agree wholeheartedly with limiting the number
> > of cycles.
> 
> So do I, but I'd still like to know what the typical values are :-)

It can buffering max 8 requests.
1 request needs max 20000 cycle to transfer.

	20000 cycle x 8 request x [4ns/cycle] = 640000[ns] = 640usec

1024usec is enough :)

Best regards
---
Kuninori Morimoto