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Date:   Tue, 21 Nov 2017 19:45:52 -0800
From:   Andy Lutomirski <luto@...nel.org>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Andy Lutomirski <luto@...nel.org>, X86 ML <x86@...nel.org>,
        Borislav Petkov <bpetkov@...e.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Brian Gerst <brgerst@...il.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Josh Poimboeuf <jpoimboe@...hat.com>
Subject: Re: [PATCH 11/16] x86/asm/64: Use a percpu trampoline stack for IDT entries

On Tue, Nov 21, 2017 at 10:57 AM, Dave Hansen <dave.hansen@...el.com> wrote:
> On 11/20/2017 09:07 AM, Andy Lutomirski wrote:
>> --- a/arch/x86/entry/entry_64.S
>> +++ b/arch/x86/entry/entry_64.S
>> @@ -560,6 +560,14 @@ END(irq_entries_start)
>>       .macro interrupt func
>>       cld
>>       ALLOC_PT_GPREGS_ON_STACK
>> +
>> +     testb   $3, CS(%rsp)
>> +     jz      1f
>> +     SWAPGS
>> +     call    switch_to_thread_stack
>> +     SWAPGS
>> +1:
>
> This looks really weird to me.  SWAPGS, switch stack, and SWAPGS again?
>
> Is this so that we can use some per-cpu data in switch_to_thread_stack,
> and then put GS back so that the normal, non-trampoline entry code can
> do its normal SWAPGS voodoo?
>
>

Yes.  I was trying to avoid totally restructuring error_entry here.

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