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Message-Id: <20171124023706.5702-9-jacob-chen@iotwrt.com>
Date: Fri, 24 Nov 2017 10:37:03 +0800
From: Jacob Chen <jacob-chen@...wrt.com>
To: linux-rockchip@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
mchehab@...nel.org, linux-media@...r.kernel.org,
sakari.ailus@...ux.intel.com, hans.verkuil@...co.com,
tfiga@...omium.org, zhengsq@...k-chips.com,
laurent.pinchart@...asonboard.com, zyc@...k-chips.com,
eddie.cai.linux@...il.com, jeffy.chen@...k-chips.com,
allon.huang@...k-chips.com, devicetree@...r.kernel.org,
heiko@...ech.de, robh+dt@...nel.org,
Jacob Chen <jacob-chen@...wrt.com>
Subject: [PATCH v2 08/11] ARM: dts: rockchip: add rx0 mipi-phy for rk3288
It's a Designware MIPI D-PHY, used by ISP in rk3288.
Signed-off-by: Jacob Chen <jacob-chen@...wrt.com>
---
arch/arm/boot/dts/rk3288.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 30677a0167fe..8b7d5a9b521f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -864,6 +864,13 @@
status = "disabled";
};
+ mipi_phy_rx0: mipi-phy-rx0 {
+ compatible = "rockchip,rk3288-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
+ clock-names = "dphy-ref", "pclk";
+ status = "disabled";
+ };
+
io_domains: io-domains {
compatible = "rockchip,rk3288-io-voltage-domain";
status = "disabled";
--
2.15.0
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