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Date:   Wed, 29 Nov 2017 11:05:46 -0800
From:   Jim Mattson <jmattson@...gle.com>
To:     Andi Kleen <ak@...ux.intel.com>
Cc:     Wanpeng Li <kernellwp@...il.com>,
        LKML <linux-kernel@...r.kernel.org>,
        kvm list <kvm@...r.kernel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH] KVM: VMX: Cache IA32_DEBUGCTL in memory

An alternative is to give the L1 guest read permission for this MSR in
the MSR permission bitmaps. It's still going to be ~80 cycles, but
that's better than the cost of a VM-exit/VM-entry round-trip.

On Wed, Nov 29, 2017 at 10:20 AM, Andi Kleen <ak@...ux.intel.com> wrote:
> Wanpeng Li <kernellwp@...il.com> writes:
>
>> From: Wanpeng Li <wanpeng.li@...mail.com>
>>
>> MSR_IA32_DEBUGCTLMSR is zeroed on VMEXIT, so it is saved/restored
>> each time during world switch. Jim from Google pointed out that
>> when running schbench in L2, vmx_vcpu_run will occupy 4% cpu time,
>> and the 25% of vmx_vcpu_run cpu time is occupied by get_debugctlmsr().
>> This patch caches the host IA32_DEBUGCTL MSR and saves/restores
>> the host IA32_DEBUGCTL msr when guest/host switches to avoid to
>> save/restore each time during world switch.
>
> FWIW i've seen this too on L2 profiles.
>
> But I haven't looked too closely, but I suspect you'll clobber global
> kernel debugger state this way.
>
> You would at least need some interface for KDB etc. to invalidate
> your cache.
>
> -Andi

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