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Date:   Wed, 29 Nov 2017 12:56:24 -0800
From:   Andi Kleen <ak@...ux.intel.com>
To:     Jim Mattson <jmattson@...gle.com>
Cc:     Wanpeng Li <kernellwp@...il.com>,
        LKML <linux-kernel@...r.kernel.org>,
        kvm list <kvm@...r.kernel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH] KVM: VMX: Cache IA32_DEBUGCTL in memory

On Wed, Nov 29, 2017 at 11:05:46AM -0800, Jim Mattson wrote:
> An alternative is to give the L1 guest read permission for this MSR in
> the MSR permission bitmaps. It's still going to be ~80 cycles, but
> that's better than the cost of a VM-exit/VM-entry round-trip.

It's a useful optimization, 80 cycles is 80 cycles.

The cache invalidation could likely be really simple, like:
have a global counter
always check the counter before and after and don't use the cache
if they don't match.
change KDB etc. to increase the counter.

-Andi

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