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Message-ID: <20171129194602.6zmjj7z5ih4ri25h@hirez.programming.kicks-ass.net>
Date: Wed, 29 Nov 2017 20:46:02 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Daniel Lustig <dlustig@...dia.com>
Cc: Alan Stern <stern@...land.harvard.edu>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
Andrea Parri <parri.andrea@...il.com>,
Luc Maranget <luc.maranget@...ia.fr>,
Jade Alglave <j.alglave@....ac.uk>,
Boqun Feng <boqun.feng@...il.com>,
Nicholas Piggin <npiggin@...il.com>,
Will Deacon <will.deacon@....com>,
David Howells <dhowells@...hat.com>,
Palmer Dabbelt <palmer@...belt.com>,
Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: Unlock-lock questions and the Linux Kernel Memory Model
On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> While we're here, let me ask about another test which isn't directly
> about unlock/lock but which is still somewhat related to this
> discussion:
>
> "MP+wmb+xchg-acq" (or some such)
>
> {}
>
> P0(int *x, int *y)
> {
> WRITE_ONCE(*x, 1);
> smp_wmb();
> WRITE_ONCE(*y, 1);
> }
>
> P1(int *x, int *y)
> {
> r1 = atomic_xchg_relaxed(y, 2);
> r2 = smp_load_acquire(y);
> r3 = READ_ONCE(*x);
> }
>
> exists (1:r1=1 /\ 1:r2=2 /\ 1:r3=0)
>
> C/C++ would call the atomic_xchg_relaxed part of a release sequence
> and hence would forbid this outcome.
That's just weird. Either its _relaxed, or its _release. Making _relaxed
mean _release is just daft.
> x86 and Power would forbid this. ARM forbids this via a special-case
> rule in the memory model, ordering atomics with later load-acquires.
Curious, I did not know about that rule. I would've thought ARM would in
fact allow it.
> RISC-V, however, wouldn't forbid this by default using RCpc or RCsc
> atomics for smp_load_acquire(). It's an "fri; rfi" type of pattern,
> because xchg doesn't have an inherent internal data dependency.
>
> If the Linux memory model is going to forbid this outcome, then
> RISC-V would either need to use fences instead, or maybe we'd need to
> add a special rule to our memory model similarly. This is one detail
> where RISC-V is still actively deciding what to do.
>
> Have you all thought about this test before? Any idea which way you
> are leaning regarding the outcome above?
FWIW I would expect the reorder to be allowed.
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