linux-kernel - Re: [PATCH v2 25/35] nds32: Build infrastructure

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAK8P3a0kvt52UTtEmE+tWHZuH_rmgTxP7+CiD9Ddwe2cJLwXTQ@mail.gmail.com>
Date:   Wed, 29 Nov 2017 09:58:53 +0100
From:   Arnd Bergmann <arnd@...db.de>
To:     Greentime Hu <green.hu@...il.com>
Cc:     Greentime <greentime@...estech.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Networking <netdev@...r.kernel.org>,
        Vincent Chen <deanbo422@...il.com>,
        DTML <devicetree@...r.kernel.org>,
        Al Viro <viro@...iv.linux.org.uk>,
        David Howells <dhowells@...hat.com>,
        Will Deacon <will.deacon@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        linux-serial@...r.kernel.org, Vincent Chen <vincentc@...estech.com>
Subject: Re: [PATCH v2 25/35] nds32: Build infrastructure

On Wed, Nov 29, 2017 at 9:39 AM, Greentime Hu <green.hu@...il.com> wrote:
> 2017-11-27 22:21 GMT+08:00 Arnd Bergmann <arnd@...db.de>:
>> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@...il.com> wrote:
>>> diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
>>> +config CPU_CACHE_NONALIASING
>>> +       bool "Non-aliasing cache"
>>> +       help
>>> +         If this CPU is using VIPT data cache and its cache way size is larger
>>> +         than page size, say N. If it is using PIPT data cache, say Y.
>>> +
>>> +         If unsure, say Y.
>>
>> Can you determine this from the CPU type?
>
> There is no cpu register to determine it. It also depeneds on page
> size and way size however page size is configurable by software.
> These codes are determined at compile time will be benefit to code
> size and performance.
> IMHO, I think it would be better to be determined here.

I meant determining it at compile time from other Kconfig symbols,
if that's possible. Do the CPU cores each have a fixed way-size?
If they do, it could be done like

menu "CPU selection"

config CPU_N15
      bool "AndesCore N15"
      select CPU_CACHE_NONALIASING

config CPU_N13
      bool "AndesCore N15"
      select CPU_CACHE_NONALIASING if PAGE_SIZE_16K

...

endmenu

and then you can use the same CPU_... symbols to make other decisions
as well, e.g. CPU specific compiler optimizations.

        Arnd