lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 29 Nov 2017 10:10:39 +0100
From:   Geert Uytterhoeven <>
To:     Arnd Bergmann <>
Cc:     Greentime Hu <>,
        Greentime <>,
        Linux Kernel Mailing List <>,
        linux-arch <>,
        Thomas Gleixner <>,
        Jason Cooper <>,
        Marc Zyngier <>,
        Rob Herring <>,
        Networking <>,
        Vincent Chen <>,
        DTML <>,
        Al Viro <>,
        David Howells <>,
        Will Deacon <>,
        Daniel Lezcano <>,
        "" <>,
        Vincent Chen <>
Subject: Re: [PATCH v2 25/35] nds32: Build infrastructure

Hi Arnd,

On Wed, Nov 29, 2017 at 9:58 AM, Arnd Bergmann <> wrote:
> On Wed, Nov 29, 2017 at 9:39 AM, Greentime Hu <> wrote:
>> 2017-11-27 22:21 GMT+08:00 Arnd Bergmann <>:
>>> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <> wrote:
>>>> diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
>>>> +       bool "Non-aliasing cache"
>>>> +       help
>>>> +         If this CPU is using VIPT data cache and its cache way size is larger
>>>> +         than page size, say N. If it is using PIPT data cache, say Y.
>>>> +
>>>> +         If unsure, say Y.
>>> Can you determine this from the CPU type?
>> There is no cpu register to determine it. It also depeneds on page
>> size and way size however page size is configurable by software.
>> These codes are determined at compile time will be benefit to code
>> size and performance.
>> IMHO, I think it would be better to be determined here.
> I meant determining it at compile time from other Kconfig symbols,
> if that's possible. Do the CPU cores each have a fixed way-size?
> If they do, it could be done like
> menu "CPU selection"
> config CPU_N15
>       bool "AndesCore N15"
> config CPU_N13
>       bool "AndesCore N15"
> ...
> endmenu
> and then you can use the same CPU_... symbols to make other decisions
> as well, e.g. CPU specific compiler optimizations.

Do you want to support multiple CPU types in a single kernel image
(I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so
you may want to invert the logic, and select CPU_CACHE_ALIASING



Geert Uytterhoeven -- There's lots of Linux beyond ia32 --

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Powered by blists - more mailing lists