lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 15 Dec 2017 23:07:41 +0100
From:   Alexandre Belloni <alexandre.belloni@...e-electrons.com>
To:     Rob Herring <robh@...nel.org>
Cc:     Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Sebastian Reichel <sre@...nel.org>, linux-pm@...r.kernel.org
Subject: Re: [PATCH v2 07/13] dt-bindings: power: reset: Document
 ocelot-reset binding

On 15/12/2017 at 14:23:32 -0600, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 04:46:12PM +0100, Alexandre Belloni wrote:
> > Add binding documentation for the Microsemi Ocelot reset block.
> > 
> > Cc: Rob Herring <robh+dt@...nel.org>
> > Cc: devicetree@...r.kernel.org
> > Cc: Sebastian Reichel <sre@...nel.org>
> > Cc: linux-pm@...r.kernel.org
> > Signed-off-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
> > ---
> >  .../devicetree/bindings/power/reset/ocelot-reset.txt    | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> > new file mode 100644
> > index 000000000000..1bcf276b04cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> > @@ -0,0 +1,17 @@
> > +Microsemi Ocelot reset controller
> > +
> > +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
> > +SoC MIPS core.
> > +
> > +Required Properties:
> > + - compatible: "mscc,ocelot-chip-reset"
> > +
> > +Example:
> > +	syscon@...70000 {
> > +		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
> > +		reg = <0x71070000 0x1c>;
> > +
> > +		reset {
> > +			compatible = "mscc,ocelot-chip-reset";
> 
> Why do you need a subnode here other than as a way to instantiate a 
> driver? Can you describe the SOFT_RST register in reg property here 
> (without having overlapping regions)?

You mean like:

reset@...7001c {
	compatible = "mscc,ocelot-chip-reset";
	reg = <0x7107001c 0x4>;
};

I guess that could work.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ