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Date:   Tue, 19 Dec 2017 11:11:42 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
Cc:     linux-snps-arc@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Vineet Gupta <Vineet.Gupta1@...opsys.com>,
        Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
        "robh+dt @ kernel . org" <robh+dt@...nel.org>
Subject: Re: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS

On 12/09, Eugeniy Paltsev wrote:
> Set initial core pll output frequency on HSDK and AXS103 via
> "assigned-clock-rates" property in device tree.  
> It will be applied at the core pll driver probing.
> 
> Eugeniy Paltsev (4):
>   ARC: [plat-hsdk]: Set initial core pll output frequency
>   ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
>   ARC: [plat-axs103]: Set initial core pll output frequency
>   ARC: [plat-axs103] refactor the quad core DT quirk code
> 

Patches look good to me.

Acked-by: Stephen Boyd <sboyd@...eaurora.org>

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