lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 20 Dec 2017 09:26:33 +0100
From:   Bartosz Golaszewski <>
To:     Andy Shevchenko <>,
        Rob Herring <>,
        Mark Rutland <>,
        Linus Walleij <>,
        Peter Rosin <>
Cc:,,, Bartosz Golaszewski <>
Subject: [PATCH v2 2/2] eeprom: at24: add support for the write-protect pin

AT24 EEPROMs have a write-protect pin, which - when pulled high -
inhibits writes to the upper quadrant of memory (although it has been
observed that on some chips it disables writing to the entire memory

On some boards, this pin is connected to a GPIO and pulled high by
default, which forces the user to manually change its state before
writing. On linux this means that we either need to hog the line all
the time, or set the GPIO value before writing from outside of the
at24 driver.

Make the driver check if the write-protect GPIO was defined in the
device tree and pull it low whenever writing to the EEPROM.

Signed-off-by: Bartosz Golaszewski <>
 drivers/misc/eeprom/at24.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index b44a3d2b2b20..4456e192681c 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -27,6 +27,7 @@
 #include <linux/regmap.h>
 #include <linux/platform_data/at24.h>
 #include <linux/pm_runtime.h>
+#include <linux/gpio/consumer.h>
  * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
@@ -77,6 +78,8 @@ struct at24_data {
 	struct nvmem_config nvmem_config;
 	struct nvmem_device *nvmem;
+	struct gpio_desc *wp_gpio;
 	 * Some chips tie up multiple I2C addresses; dummy devices reserve
 	 * them for us, and we'll use them with SMBus calls.
@@ -442,12 +445,14 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
 	 * from this host, but not from other I2C masters.
+	gpiod_set_value_cansleep(at24->wp_gpio, 0);
 	while (count) {
 		int status;
 		status = at24_regmap_write(at24, buf, off, count);
 		if (status < 0) {
+			gpiod_set_value_cansleep(at24->wp_gpio, 1);
 			return status;
@@ -457,6 +462,7 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
 		count -= status;
+	gpiod_set_value_cansleep(at24->wp_gpio, 1);
@@ -604,6 +610,11 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	at24->num_addresses = num_addresses;
 	at24->offset_adj = at24_get_offset_adj(chip.flags, chip.byte_len);
+	at24->wp_gpio = devm_gpiod_get_optional(&client->dev,
+						"wp", GPIOD_OUT_HIGH);
+	if (IS_ERR(at24->wp_gpio))
+		return PTR_ERR(at24->wp_gpio);
 	at24->client[0].client = client;
 	at24->client[0].regmap = devm_regmap_init_i2c(client, &regmap_config);
 	if (IS_ERR(at24->client[0].regmap))

Powered by blists - more mailing lists