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Message-ID: <20171222002402.GN7997@codeaurora.org>
Date:   Thu, 21 Dec 2017 16:24:02 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Abhishek Sahu <absahu@...eaurora.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Rob Herring <robh+dt@...nel.org>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v2 06/11] clk: qcom: ipq8074: add PCIE, USB and SDCC
 clocks

On 12/13, Abhishek Sahu wrote:
> - It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC
>   AXI and PIPE clocks.
> - It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE,
>   SYS NOC, mock UTMI and master clocks.
> - It has 2 instances of SDCC which uses APSS and AHB clock.
>   SDCC1 requires ICE core clock also.
> - All the PIPE clocks are external clocks which will be
>   registered in clock framework by PHY drivers. The enabling
>   and disabling of PIPE RCG clocks are dependent upon PHY
>   initialization sequence so BRANCH_HALT_DELAY flag is required for
>   these clocks.
> 
> Signed-off-by: Abhishek Sahu <absahu@...eaurora.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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