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Message-ID: <20171222002354.GL7997@codeaurora.org>
Date:   Thu, 21 Dec 2017 16:23:54 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Abhishek Sahu <absahu@...eaurora.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Rob Herring <robh+dt@...nel.org>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v2 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider
 width

On 12/13, Abhishek Sahu wrote:
> GPLL0 uses 4 bits post divider which should be specified
> in clock driver structure.
> 
> Signed-off-by: Abhishek Sahu <absahu@...eaurora.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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