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Message-ID: <1514994345-2471-1-git-send-email-rasmus.villemoes@prevas.dk>
Date: Wed, 3 Jan 2018 16:45:45 +0100
From: Rasmus Villemoes <rasmus.villemoes@...vas.dk>
To: Shawn Guo <shawnguo@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Russell King <linux@...linux.org.uk>
CC: Rasmus Villemoes <rasmus.villemoes@...vas.dk>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v2] ARM: dts: ls1021a: add nodes for on-chip ram
Although the two nodes constitute one contiguous 128K region, still
describe them separately:
- That's how they are described in the reference manual: "Each OCRAM
occupies a 64 KB of address region...", and the names ocram1 and
ocram2 are also as used in the manual.
- The two areas are treated differently by the boot ROM code: OCRAM2 is
zero-initialized, while, again quoting the RM, "software must perform
the zero initialization of OCRAM1."
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@...vas.dk>
---
v2: add changelog explaining the split in two nodes.
arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 96aa7752dd0d..7bb5896b3726 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -748,5 +748,21 @@
<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ ocram1: sram@...00000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x10000000 0x10000>;
+ };
+
+ ocram2: sram@...10000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x10010000 0x10000>;
+ };
};
};
--
2.7.4
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