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Message-ID: <CAMzpN2hi9QkamCX2QvS8ukwJQtGKShLs6V2RmM8VjXF+8PdDxQ@mail.gmail.com>
Date: Fri, 5 Jan 2018 11:35:24 -0500
From: Brian Gerst <brgerst@...il.com>
To: Tom Lendacky <thomas.lendacky@....com>
Cc: "the arch/x86 maintainers" <x86@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Peter Zijlstra <peterz@...radead.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Dave Hansen <dave.hansen@...el.com>,
Borislav Petkov <bp@...en8.de>,
Thomas Gleixner <tglx@...utronix.de>,
Tim Chen <tim.c.chen@...ux.intel.com>,
Greg Kroah-Hartman <gregkh@...ux-foundation.org>,
David Woodhouse <dwmw@...zon.co.uk>,
Paul Turner <pjt@...gle.com>
Subject: Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction
On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky <thomas.lendacky@....com> wrote:
> To aid in speculation control, make LFENCE a serializing instruction.
> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families
> that support LFENCE do not have this MSR. For these families, the LFENCE
> instruction is already serializing.
Does this require a microcode update?
--
Brian Gerst
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