linux-kernel - Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of MFENCE

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Message-ID: <alpine.DEB.2.20.1801081611180.1735@nanos>
Date:   Mon, 8 Jan 2018 16:15:35 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Tom Lendacky <thomas.lendacky@....com>
cc:     Andrew Cooper <andrew.cooper3@...rix.com>, bp@...en8.de,
        dwmw@...zon.co.uk, gregkh@...ux-foundation.org, pjt@...gle.com,
        mingo@...nel.org, linux-kernel@...r.kernel.org, hpa@...or.com,
        tim.c.chen@...ux.intel.com, torvalds@...ux-foundation.org,
        peterz@...radead.org, dave.hansen@...el.com,
        linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of
 MFENCE_RDTSC

On Mon, 8 Jan 2018, Tom Lendacky wrote:
> On 1/8/2018 5:10 AM, Thomas Gleixner wrote:
> >>> Second thoughts on that. As pointed out by someone in one of the insane
> >>> long threads:
> >>>
> >>> What happens if the kernel runs as a guest and
> >>>
> >>>   - the hypervisor did not set the LFENCE to serializing on the host
> >>>
> >>>   - the hypervisor does not allow writing MSR_AMD64_DE_CFG
> >>>
> >>> That would bring the guest into a pretty bad state or am I missing
> >>> something essential here?
> >>
> >> What I did in Xen was to attempt to set it, then read it back and see. 
> >> If LFENCE still isn't serialising, using repoline is the only available
> >> mitigation.
> >>
> >> My understanding from the folk at AMD is that retpoline is safe to use,
> >> but has higher overhead than the LFENCE approach.
> 
> Correct, the retpoline will work, it just takes more cycles.
> 
> > 
> > That still does not help vs. rdtsc_ordered() and LFENCE_RDTSC ...
> 
> Ok, I can add the read-back check before setting the feature flag(s).
>
> But... what about the case where the guest is a different family than
> hypervisor? If we're on, say, a Fam15h hypervisor but the guest is started
> as a Fam0fh guest where the MSR doesn't exist and LFENCE is supposed to be
> serialized?  I'll have to do a rdmsr_safe() and only set the flag(s) if I
> can successfully read the MSR back and validate the bit.

But that still does not make this patch correct and neither the next one.

If you cannot set the flag and you cannot prove that you run on bare metal,
then you still need the MFENCE_RDTSC variant as you have no idea what the
underlying hypervisor is and how it has the LFENCE configured.

Thanks,

	tglx