[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20180109102747.GJ26312@b29396-OptiPlex-7040>
Date: Tue, 9 Jan 2018 18:27:47 +0800
From: Dong Aisheng <dongas86@...il.com>
To: Anson Huang <Anson.Huang@....com>
Cc: shawnguo@...nel.org, kernel@...gutronix.de, fabio.estevam@....com,
robh+dt@...nel.org, mark.rutland@....com, linux@...linux.org.uk,
rjw@...ysocki.net, viresh.kumar@...aro.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
linux-imx@....com
Subject: Re: [PATCH V3 2/2] cpufreq: imx6q: add 696MHz operating point for
i.mx6ul
On Mon, Jan 08, 2018 at 10:04:51AM +0800, Anson Huang wrote:
> Add 696MHz operating point for i.MX6UL, only for those
> parts with speed grading fuse set to 2b'10 supports
> 696MHz operating point, so, speed grading check is also
> added for i.MX6UL in this patch, the clock tree for each
> operating point are as below:
>
> 696MHz:
> pll1 696000000
> pll1_bypass 696000000
> pll1_sys 696000000
> pll1_sw 696000000
> arm 696000000
> 528MHz:
> pll2 528000000
> pll2_bypass 528000000
> pll2_bus 528000000
> ca7_secondary_sel 528000000
> step 528000000
> pll1_sw 528000000
> arm 528000000
> 396MHz:
> pll2_pfd2_396m 396000000
> ca7_secondary_sel 396000000
> step 396000000
> pll1_sw 396000000
> arm 396000000
> 198MHz:
> pll2_pfd2_396m 396000000
> ca7_secondary_sel 396000000
> step 396000000
> pll1_sw 396000000
> arm 198000000
>
> Signed-off-by: Anson Huang <Anson.Huang@....com>
> Reviewed-by: Fabio Estevam <fabio.estevam@....com>
For this series:
Acked-by: Dong Aisheng <aisheng.dong@....com>
Regards
Dong Aisheng
Powered by blists - more mailing lists