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Message-Id: <20180112012755.20495-9-chris.packham@alliedtelesis.co.nz>
Date: Fri, 12 Jan 2018 14:27:55 +1300
From: Chris Packham <chris.packham@...iedtelesis.co.nz>
To: linux@...linux.org.uk, bp@...en8.de, jlu@...gutronix.de
Cc: Chris.Packham@...iedtelesis.co.nz,
thomas.petazzoni@...e-electrons.com, kernel@...gutronix.de,
gregory.clement@...e-electrons.com,
Chris Packham <chris.packham@...iedtelesis.co.nz>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v4 8/8] EDAC: armada_xp: Add support for more SoCs
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
---
drivers/edac/armada_xp_edac.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 70cff01afc8d..03a18b54467a 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
axp_mc_read_config(mci);
+ /* These SoCs have a reduced width bus */
+ if (of_machine_is_compatible("marvell,armada380") ||
+ of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+ drvdata->width /= 2;
+
/* configure SBE threshold */
/* it seems that SBEs are not captured otherwise */
writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
--
2.15.1
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