linux-kernel - Re: [PATCH v2] x86/microcode/intel: Extend BDW late-loading with LLC size check

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Message-ID: <20180116201158.7mu6pj6ynqrfdxe4@agluck-desk>
Date:   Tue, 16 Jan 2018 12:11:58 -0800
From:   "Luck, Tony" <tony.luck@...el.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Jia Zhang <zhang.jia@...ux.alibaba.com>,
        "hmh@....eng.br" <hmh@....eng.br>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] x86/microcode/intel: Extend BDW late-loading with LLC
 size check

On Tue, Jan 16, 2018 at 09:01:49PM +0100, Borislav Petkov wrote:
> On Tue, Jan 16, 2018 at 05:24:27PM +0000, Luck, Tony wrote:
> > > I'll look for someone who can confirm the 2.5MB/core detail.
> > 
> > Ok ... re-read the erratum.  The 2.5MB/core is clear.  The E5+E7 is clear.
> > 
> > No mention of the platform ID, but Jia is dropping that part.
> > 
> > Boris ... what specific questions remain?
> 
> This magic:
> 
> 	llc_size_per_core(c) > 2621440
> 
> as a reliable detection characteristic whether the patch is good to
> apply late. There must be a more reliable way to detect that.
> 
> Also, the testing order is:
> 
>            llc_size_per_core(c) > 2621440 &&
>             c->microcode < 0x0b000021) {
> 
> so if the LLC size per core check fails, the microcode revision being <
> 0x0b000021 doesn't matter. I.e., on machines with LLC-per-core < 2.5M,
> we can update even with revisions < 0x0b000021.
> 
> Is that ordering correct?

I think so. The erratum (see below) says the problem only occurs
on the large-cache SKUs.  So we only need to avoid the update if
we are on a big cache SKU that is also running old microcode.

> Also, this heuristic is not documented in the public doc AFAICT - I'm
> guessing that'll change soon...?

Here's what I see in the public doc. for BDF90:

    Problem: An uncorrectable error (IA32_MC3_STATUS.MCACOD=0400 and
    IA32_MC3_STATUS.MSCOD=0080) may be logged for processors that have more
    than 2.5MB last-level-cache per core on attempting to load a microcode
    update or execute an authenticated code module. This issue does not
    occur with microcode updates with a signature of 0x0b000021 and greater.

-Tony